In recent years, phase-change memories have been developing (refer to, for example, PTL 1). In phase-change memories, information is memorized by changing and recording the resistance of an information memory element of a memory cell.
The mechanism is as follows. When a current is allowed to flow between a bit line and a source line by turning a cell transistor to the on-state, heat is generated in a heater, which is a high-resistance element. Chalcogenide glass (GST: Ge2Sb2Te5) that contacts this heater is melted, thereby causing a transition of the state of the chalcogenide glass. When the chalcogenide glass is melted at a high temperature (by supplying a high current) and cooled at a high speed (by stopping the current), the chalcogenide glass transitions to an amorphous state (reset operation). When the chalcogenide glass is melted at a relatively low high-temperature (by applying a low current) and slowly cooled (by gradually decreasing the current), the chalcogenide glass is crystallized (set operation). With this mechanism, at the time of reading out information, information of “0” or information of “1” is determined on the basis of the case where the amount of current flowing between the bit line and the source line is large (low resistance=crystal state) and the case where the current flowing between the bit line and the source line is small (high resistance=amorphous) (refer to, for example, PTL 1).
In this case, for example, the reset current is very large, namely, 200 μA. In order to make the reset current large in this manner and to allow this current to flow to a cell transistor, the size of a memory cell has to be very large. In order to allow a large current to flow, a selection element such as a bipolar transistor or a diode can be used (refer to, for example, PTL 1).
Diodes are two-terminal elements. Therefore, in order to select a memory cell, when one source line is selected, currents of all memory cells connected to the one source line flow in the one source line. Consequently, the IR drop in the resistance of the source line increases.
On the other hand, bipolar transistors are three-terminal elements. However, since a current flows in a gate, it is difficult to connect a large number of transistors to a word line.
A surrounding gate transistor (hereinafter referred to as “SGT”) having a structure in which a source, a gate, and a drain are arranged in a direction perpendicular to a substrate and a gate electrode surrounds a pillar-shaped semiconductor layer has been proposed (refer to, for example, PTL 2). Since the source, the gate, and the drain are arranged in a direction perpendicular to the substrate, a small cell area can be realized.